SiOn/Ta2O5/TiN Gate-Stack Transistor with 1.8nm Equivalent SiO2 Thickness

SiON/Ta2O5 stacked gate dielectric exhibits 3-5 orders smaller leakage current than SiO2 at 1.8nm, while the transistor characteristics such as mobility, Id-Vg, and Id-Vd, are similar to those of SiO2 transistor. N-channel MOSFET with equivalent SiO2 thickness down to 1.8nm (1.4nm equivalent due to elimination of poly-Si depletion) is demonstrated. Process effects are also studied for optimum process condition. INTRODUCTION The gate dielectric thickness must be reduced in order to maintain acceptable short-channel effects as the channel length of the MOSFET is reduced and to maximize drain current, Id. The fundamental limit to the scaling of thin SiO2 is the large leakage current due to direct tunneling [1,2]. When the SiO2 thickness is reduced below 2nm, alternative highpermittivity dielectrics such as Ta2O5 must be considered. Ta2O5 has been studied as the capacitor dielectric in gigabit DRAMs [3-5]. MOSFET with Ta2O5 dielectric of 2.8nm equivalent thickness has been reported previously [6]. In this paper, for the first time, we report on MOSFETs with SiON/Ta2O5/TiN gate stack in various annealing conditions for process window study as the Fig. 1 Gate leakage current of SiO2 and SiON/Ta2O5 MOSFETs. The lower leakage current of the SiON/Ta2O5 device is a major benefit, especially for memory applications. equivalent SiO2 thickness scales down to 1.8nm/1.4nm. EXPERIMENT N-channel MOSFETs were fabricated on p-type 10-20 ohm-cm Si wafers using LOCOS isolation. After active area patterning and LOCOS processing, the wafers proceeded through the gate-stack formation processes. First, nitridation of the silicon surface was performed in a Heatpulse 8108 system with a rapid thermal process (RTP) in NH3 ambient at 800° C for 30sec. Then, 6nm Ta2O5 film was deposited by chemical vapor deposition (CVD) with Ta(OC2H5)5 and O2 at 420° C, 400mT by DSM9800 (Lam Research). After Ta2O5 deposition, the samples were annealed at 800° C for 30sec using RTP in O2 ambient [7,8]. In-situ N-doped CVD polysilicon over sputter-deposited 60nm TiN was used for the gate electrode formation. After the polysilicon deposition, the wafers were annealed by RTP. Following gate poly patterning, the source and drain regions were formed with an arsenic ion implant of 5×10/cm at 60keV and a 30min anneal in N2 at 800° C. Fig. 2 C-V characteristics of SiO2 and 1.8nm SiON/Ta2O5 transistors. Lines represent theory including quantum effect in the inversion layer and the gate depletion. The C-V model is a useful tool for extracting the equivalent SiO2 thickness. -2 -1 0 1 0.0 0.3 0.6 0.9 1.2 1.5